An electronic thin-film device is typically encapsulated to protect it from, for example, moisture and/or oxygen in order to prevent or reduce degradation and device failure. The device contains multiple elements and these elements are typically connected to external devices. In order to connect to external devices, traces from the elements are routed to the perimeter of the electronic thin-film device where these traces are connected to the external device using, for example, one or more flex connectors, a printed circuit board (“PCB”), or a chip-on glass driver.
Examples of the electronic thin-film device are: an active or passive matrix OLED display, an active or passive matrix OLED light source, an active or passive matrix inorganic electroluminescent display, an organic or inorganic detector array, an organic or inorganic solar cell array, or an organic or inorganic thin-film transistor array. These devices are know in the art and are discussed in, for example: U.S. Pat. No. 6,069,443 entitled “Passive Matrix OLED Display”; U.S. Pat. No. 5,733,381 entitled “Thin-Film Solar Cell Array and Method of Manufacturing Same”; U.S. Pat. No. 6,459,208 entitled “Active Matrix Electroluminescent Display Device”; and U.S. Pat. No. 6,211,534 entitled “Thin Film Transistor Array and Method for Fabricating the Same”. All of these patents are incorporated by reference herein in their entirety.
An active area of the electronic thin-film device has a boundary that is the perimeter of the combination of multiple electronic thin-film elements. Each electronic thin-film element includes at least two electrodes and one or more semiconductive material between the electrodes in which charge carriers move between electrodes via the material when the element is activated. Examples of electronic thin-film elements are: light emitting element (e.g., an OLED used as a pixel in a display or as a light source element in a light source), a light detector element, a solar cell element, or a thin-film transistor element. These elements, in general, are know in the art and are discussed in, for example: U.S. Pat. No. 5,457,565 entitled “Organic Electroluminescent Device”; U.S. Pat. No. 6,483,099 entitled “Organic Diodes with Switchable Photosensitivity”; U.S. Pat. No. 6,485,884 entitled “Method for Patterning Oriented Materials for Organic Electronic Displays and Devices”; and U.S. Pat. No. 4,963,196 entitled “Organic Solar Cell”. All of these patents are incorporated by reference herein in their entirety.
FIG. 1 shows a schematic of a prior art passive-matrix OLED display 103. The display 103 includes an active area 115 on a substrate 121. The active area 115 includes columns of electrodes and rows of electrodes. The rows of electrodes are perpendicular to the columns of electrodes. An organic layer is between the columns of electrodes and the rows of electrodes. OLED pixels are formed at the intersections of the columns of electrodes and the rows of electrodes. Row conductive traces 106 are coupled to the rows of electrodes and column conductive traces 109 are coupled to the columns of electrodes. The row conductive traces 106 and the column conductive traces 109 are routed to only one side of the display 103; for example, in FIG. 1, these traces are routed to the bottom-end. The other end of the traces is routed to a contact pad 118 that is used to couple the traces to a connector such as a flex connector. The connector is used, for example, to couple the display 103 to an external device such as a display driver (e.g., a row driver and a column driver). A perimeter seal 112 is deposited on the substrate 121 so that an encapsulation lid (e.g., a glass lid, a metal cap, or a PCB) can be glued to the substrate in order to seal (e.g., encapsulate) the display 103. Because of the encapsulation lid, the connector can be attached only after substrate singulation.
FIG. 2 shows another schematic of the prior art passive-matrix OLED display 103. In FIG. 2, multiple OLEDs are fabricated on the substrate 121 of the display 103. The multiple OLEDs together form the active area 115 of the display 103. An encapsulation lid (e.g., a glass lid, a metal cap, or a PCB)(not shown) is glued to the substrate 121 using the perimeter seal 112 in order to encapsulate the display 103. The row and column traces (not shown) are routed to a contact pad 118 that is used to couple the traces to a connector such as a flex connector.
FIG. 3 shows a side view of the prior art passive-matrix OLED display 103. In FIG. 3, the perimeter seal 112 is deposited around the active area 115. The encapsulation lid 124 is placed on the perimeter seal 112 to encapsulate the active area.
Referring to FIG. 1, the conductive traces are routed to one side thus the traces originating from the other sides are relatively long. To reduce the overall usage of space on the substrate 121, the pitch between conductive traces is very fine and if many traces are used, the pitch between the long traces as it is routed to the one side is even smaller and the pitch between the traces at the contact pad is also even smaller. Having a fine pitch between traces increases the resistance of the traces and thus higher voltage drivers are used resulting in greater power consumption and increased resistive heating power loss in the traces. The increase in resistance and voltage results in fewer number of traces being used in the display and hence the number of rows and columns are reduced resulting in reduced display resolution and size. Having a fine pitch between traces increases the likelihood that one trace will electrically short another trace. In addition, the fine pitch can cause electrochemical reactions or electromigration that also increases the likelihood of an electrical short.
The area occupied by the routing of the conductive traces to the one side and the area occupied by the perimeter seal 112 is typically several millimeters. If a 400 mm by 400 mm mother glass on which an array of 10×10=100 displays is to be fabricated, the additional use of several millimeters for each display significantly reduces the number of displays per mother glass (for example, the reduction in the number of displays can be between 10% to 20%). If the number of displays per mother glass is reduced, then the cost per display increases.
The increase in the space occupied due to routing the traces to only one side and due to the perimeter seal 112 results in reduced design freedom. Thin-film electronic devices typically use precise top electrode deposition techniques, and typically have contact via holes inserted using, for example, laser ablation. These processes have a manufacturing tolerance resulting in an increase in the display size to account for the tolerance. If the space occupied by the conductive traces and the perimeter seal 112 is reduced, then the size of the display need not be increased to account for these tolerances. In addition, the availability of more space on the substrate 121 allows for greater tolerances for processes such as top electrode deposition and via hole insertion thus resulting in increased process yield and robustness of manufacturing.
For the foregoing reasons, there exists a need to fabricate, encapsulate and connect to the electronic thin-film device such that the space occupied on the substrate is minimized, device reliability is increased, and power consumption is reduced.